Impacts of EOT Scaling of ZrO x /HfO x Dielectric on Monolayer WSe 2 Top-Gate p-MOSFETs

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This work demonstrates the two-step elevated-temperature atomic layer deposit (ALD) process of bilayer ZrOₓ/HfOₓ relatively higher-κ dielectrics reported on chemical vapor deposit (CVD) monolayer (1L) WSe2for top-gate dielectric. Top-gated 1L-WSe2pFETs with a low subthreshold swing (S.S. ~60 mV/dec) are achieved at a low equivalent oxide thickness (EOT) of 0.8 nm. By scaling the physical thickness of this two-step bilayer ZrOₓ/HfOₓ dielectric with the pinhole-free AlOₓ nucleation layer down to 2 nm, the proposed gate stack exhibits a high effective dielectric constant (εeff~14) and strong reliability (breakdown field EBD~21 MV/cm) at the scaled EOT. This breakthrough in gate dielectric integration on p-type 1L-WSe2enables balanced n/p performance for 2D-channel devices and enhances the feasibility of future low-power consumption CMOS applications.

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