A Novel Dual-Sided Method for Precise Resistance and Capacitance Partition in GAA Transistors With Backside Contacts

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With advanced logic transistor evolving rapidly and getting more complex, precise device’s resistance and capacitance partition is of growing significance in cutting-edge logic technology development, especially for the performance ramping. Unfortunately, the conventional wafer frontside test method faces intrinsic limitations in separating each resistance or capacitance component accurately. In this work, we proposed for the first time a dual-sided test method that fully exploits backside contact (BSC) to precisely partition the resistances of contact, S/D epitaxy and each channel as well as the gate-to-S/D metal capacitance (${C}_{\text {gmd}}\text {)}$for future gate all around (GAA) nanosheet field-effect transistor (NSFET) with BSC. A well-calibrated technology computer-aided design (TCAD) deck was built to conduct a series of TCAD experiments and benchmark the method. TCAD-vs-test comparisons confirm an error below 10%, proving the method’s great accuracy, reliability, and robustness across a broader range of device geometries and features. In addition, the proposed capacitance partition method was further verified through TCAD, providing a unique way to understand device parasitic. This work provides a novel, effective, and extendable test method for resistance and capacitance partition, delivering powerful guidance for the future advanced logic technology node development.

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