A Broadcast-Based Fully Parallel Test Architecture for Processing-in-Memory

Le résumé fourni par la source

For the improvement of processing-in-memory (PIM) yield, an efficient test architecture for the processing unit (PU) is necessary. While scan-based tests can achieve high test coverage, the incurred test cost in terms of area overhead and test time is high. Therefore, to improve test coverage with low test cost, we propose a broadcast-based test architecture that leverages the PU characteristic, where identical modules are repeatedly implemented. By broadcasting test patterns to identical modules and comparing their outputs, the fully parallel test is achieved, where the primary output observation is not necessary. Experimental results show that the proposed architecture significantly reduces area overhead and test time, while a loss of test coverage is less than 1% compared to the full scan structure.

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