A low-power 9T SRAM with half-selection resilient in carbon nanotube field-effect transistor technology for battery-operated systems

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Abstract This paper presents a novel low-power, read-disturbance-free, and half-selection-free 9T SRAM cell based on carbon nanotube field-effect transistor (CNTFET) technology. The proposed SRAM cell features a single-ended, decoupled read path, and a write-assist mechanism to enhance both read static noise margin (RSNM) and write static noise margin (WSNM). Extensive simulations demonstrate significant improvements in stability, power efficiency, and process variation resilience. At a supply voltage of 0.5 V, the proposed SRAM cell exhibits a 105.65% higher RSNM than the traditional 6T SRAM cell, along with reductions in read and write power by up to 63.98% and 57.60%, respectively. Additionally, Monte-Carlo analysis confirms robust performance under process variations, with minimal variability in RSNM, WSNM, and leakage power. The proposed design is particularly suited for low-voltage, high-density memory applications, offering a balanced trade-off between speed, stability, and energy efficiency.

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