High-speed/reliability multilevel FeFET memory with atomic-layer-deposited TiO 2 channel and HZO ferroelectric

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Abstract Atomic-layer-deposited TiO 2 -/hafnium zirconium oxide (HZO)-based ferroelectric field-effect transistors (FeFETs) have been fabricated for non-volatile memory applications through a single-step post-device annealing process. In this work, the TiO 2 layer serves as both the conductive channel and capping layer, promoting the formation of ferroelectric phase in HZO after annealing at ≥ 350 °C. A memory window of 2 V is obtained under optimized annealing temperature of 600 °C, accompanied by a minimum subthreshold swing and a maximum drain current, and the resulting maximum double remanent polarization (2 ) is 25.2 μ C/cm 2 . Further, the TiO 2 FeFET memory with a channel length of 80 nm shows fast program/erase speeds (10 ns under 3 V /4.5 V ), yielding a current window over 10 2 . Stable 2-bit retention and endurance exceeding 10 9 cycles at 85 °C are achieved. These results suggest the TiO 2 /HZO FeFET memory is promising for low-power embedded non-volatile memory (eNVM) and monolithic three-dimensional (3D) integration applications.

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