A 9.1% Peak Efficiency 243-318 GHz Frequency Doubler Using an In-Core Stepped-Impedance Network in 22 nm FDSOI CMOS

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This paper presents a high-efficiency wideband frequency doubler operating above 240 GHz fabricated in a 22 nm FDSOI CMOS technology. The doubler core is based on a modified pseudo-differential common source topology. We propose an in-core stepped-impedance network, which serves several purposes: a) wideband large-signal core impedance matching for the second-harmonic (H2); b) acting as a reflector for the fundamental harmonic (H1), boosting the H1 amplitude at the gates and thereby enhancing the nonlinearity-based$\mathbf{H}_{2}$generation at the drains; c) inherent power summation for H2 (in common-mode) and suppression of H1 (in differential mode). The presented doubler achieves a low conversion loss of 6.5 dB at 290 GHz in measurement. With a low DC power consumption$\mathrm{P}_{\text{DC}}$of 10.8 mW at a$P_{\text {sat }}$of 3.35 dBm, this results in an outstanding peak efficiency$\eta_{\text {tot }}$of$\mathbf{9. 1 \%}$at$\mathbf{2 9 0 ~ G H z}$. Additionally, the circuit achieves a very wide$3-\text{dB}$fractional bandwidth of 26.7 %. The circuit occupies a minimal active chip area of only$0.032 ~\text{mm}^{2}$. To the best of the authors' knowledge, this is the highest reported peak efficiency for a frequency doubler at frequencies around 300 GHz in an advanced CMOS node.

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