A 32×32 16-bit integer matrix multiplication hardware acceleration design and evaluation on 45nm PDK

Le résumé fourni par la source

This paper presents the design and implementation of a 32×32 matrix multiplier using 16-bit integer data, targeted for hardware acceleration applications. The design is described in VHDL and synthesized using Cadence EDA toolchain with a FreePDK45nm CMOS process for ASIC implementation. The proposed architecture employs pipelining and parallelism techniques to optimize speed and power consumption. Post-layout Place and Rout results demonstrate that the design achieves a maximum operating frequency of 200 MHz, occupies an area of 107,240 μm², and consumes 350.24 mW of power under typical conditions. The experimental results validate the feasibility of the design for high-performance embedded systems, edge devices and digital signal processing applications.

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