Spike-Count Reduction Techniques for Low Power Spiking Neural Networks

Le résumé fourni par la source

Spiking neural network (SNN) has demonstrated its great potential in low-power neuromorphic applications. In SNN, computation activities are associated with the arrival and firing of spikes, its power consumption is directly correlated with the number of spikes propagated in the network. In this paper, we explore two methods to reduce the spike-count in the network, aiming to reduce the power consumption of SNN. We use Poisson distribution function in the input layer and through adjusting the correlation (called the gain in the paper) between the probability of spike generation and input values, the number of spikes in the input layer can be reduced to only 20% of the baseline model with the accuracy degradation of less than 1%. We also exploit the leaky-integrate-and-fire (LIF) mechanism and use the refractory period to reduce the generation of spikes from the neurons in the hidden layers. Through this method, the spike-count is reduced by 20% $$\sim $$ 50% while the performance degradation is still less than 1%. These two spike-count reduction techniques are implemented in Verilog RTL; the power simulation results demonstrate significant power reduction in performing SNN computations. We further discovered that for different network architectures, these two techniques have different trade-offs to achieve optimal spike-count reduction while maintaining satisfactory results. Compared with other spike-count reduction techniques, the proposed scheme is efficient and straightforward for hardware implementation, making it well-suited for edge computing scenarios.

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