Enhanced Performance SRAM Design using 7nm FinFET Technology: Optimization of Propagation Delay and Power Consumption

Le résumé fourni par la source

This research implements a 7nm FinFET-based 7T SRAM cell, designed using Xschem and simulated with Ngspice. The primary emphasis of this research aimed at reducing the propagation delay and power consumption. Simulation results reveal that the proposed design offers significant improvements over traditional SRAM cells. Compared to the conventional 7nm 6T SRAM, the 7T cell achieves reductions of 9.20% in read power, 7.72% in write power, and a substantial 32.46% decrease in leakage power. Additionally, read and write delays are reduced by 10.23% and 4.21%, respectively. When benchmarked against the older 130nm 6T SRAM, the 7nm 7T design demonstrates up to 44.00% lower leakage power and over 16% reduction in dynamic power metrics, albeit with a slight trade-off in write delay. These results underscore the energy efficiency and speed advantages of FinFET-based SRAM, establishing it as a promising candidate for next-generation memory applications. Future research can explore further optimizations to enhance performance under varying operating conditions.

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