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Design and implementation of an enhanced anti-SAT framework for robust protection against SAT-based attacks on logic-locked circuits

1Citations signalées, ce qui n’est pas une note de qualité
2Institutions déclarées
2Pays d’affiliation déclarés

Rattachement africain : in, kr. Niveau de preuve : code pays fourni par la source.

Le résumé fourni par la source

Ensuring the security of Integrated Circuits (ICs) against reverse engineering and unauthorized access is challenging. They are vulnerable to Satisfiability (SAT)-based attacks, which can systematically reduce the search space by effectively bypassing conventional logic locking techniques. The existing methods are vulnerable to skew in the algorithms or signal probability skew-based removal attacks or takes required overhead. To fill this gap, we propose a new compact lightweight Anti-SAT block (ASB) and its obfuscation approach together with a Challenge-Response Authentication Framework (CRAF) that exponentially increases IC security by making SAT solver complexity infeasible to attackers through decoy keys. The Anti-SAT Block (ASB) includes decoy keys which exponentially increase the complexity of SAT solver, and from which true keys cannot be recovered. Incorporation of ASB in a locked circuit thwarts vulnerable SAT attacks. The novelty is that the proposed ASB design with obfuscation technique not only provides effective protection against SAT attacks but also provides ATPG-based cost-effective secured locking mechanism with reduced overhead. The challenge-response module also assures that access is valid, by authenticating it and preventing the circuit from being opened by unauthorized users. The proposed novelty achieves a high fault detection efficiency of 98% and test pattern coverage of 99% with very low power down to 48% and area overhead of 12% which is suitable for high-security applications. This solution provides superior resistance to SAT-based attacks that provide resistance over the traditional key gate-based logic locking techniques and protect sensitive ICs from advanced hardware threats. This work demonstrates the strength of the Anti-SAT and authentication framework in protecting modern IC designs and provides promise as a solution for critical applications in defense, finance, and other security-sensitive industries.

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Le contrôle bibliographique ouvert

DOI retrouvé dans Crossref DOI retrouvé ; titre concordant.

Titre Crossref
Design and implementation of an enhanced anti-SAT framework for robust protection against SAT-based attacks on logic-locked circuits
Date Crossref
01/09/2025
Éditeur
Elsevier BV
Type
journal-article

Ce recoupement confirme des métadonnées liées au DOI. Il ne confirme ni la méthode ni les conclusions de l’étude, et il ne compte pas comme une seconde source scientifique indépendante.

Où se fait cette recherche

  • Amrita Vishwa Vidyapeetham pays non établi dans la notice
    Université ou école supérieure
  • Chung-Ang University Department of Energy Systems Engineering pays non établi dans la notice
    Université ou école supérieure
  • Amrita School of Engineering Department of Electronics and Communication Engineering pays non établi dans la notice
    Université ou école supérieure
  • Tessolve Semiconductors Private Limited pays non établi dans la notice
    Institution
  • Sri Krishna College of Technology Department of Electronics and Communication Engineering pays non établi dans la notice
    Université ou école supérieure

Amrita Vishwa Vidyapeetham, Department of Energy Systems Engineering — Chung-Ang University et Department of Electronics and Communication Engineering — Amrita School of Engineering, avec 2 autres affiliations.

Une affiliation ne permet pas de déduire la nationalité d’un auteur.

Les sujets associés

Physical Unclonable Functions (PUFs) and Hardware SecurityCryptographic Implementations and SecurityIntegrated Circuits and Semiconductor Failure Analysis

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