Design of 4-Bit Multiplier Using Modified Gate Diffusion Input Technology for Low Power Applications

Le résumé fourni par la source

Multipliers are widely used in digital circuits for countless arithmetic operations and are critical components in many very large scale integration systems. The multiplication process is one of the basic processes in digital equipment, and hardware multipliers play a key role in facilitating efficient data processing and fast computing. The demand for multipliers that are characterised by low energy consumption and high performance has stimulated the development of a variety of design methods, with particular emphasis on surface and energy efficiency. In this research we introduce a modified gate-diffusion input (MGDI) cell architecture for a 4-bit field multiplier that shows a higher energy efficiency than traditional designs of multipliers. The MGDI-based multiplier achieves a significant reduction in energy consumption (1.109861 mW) while maintaining the necessary operational efficiencies. The 4-bit MGDI multiplier is carefully designed using Tanner EDA tools, and extensive simulations have been performed to demonstrate its performance.

Ce résumé expose les affirmations des auteurs. BNTIC ne l’interprète pas comme une validation indépendante des résultats.