Phase change memory programming circuit with improved speed

Le résumé fourni par la source

Abstract Phase change memory (PCM) is considered one of the most promising next-generation non-volatile memory types for storage-class memory due to its many advantages, including ultrafast programming, long data retention, high storage density, low power consumption, and compatibility with standard CMOS processes. However, in conventional PCM programming circuits, the first programming operation after power-on suffers from a slow rise time in the programming pulse due to the lack of bias voltage pre-charging in the current source circuit, which leads to reduced consistency in the programming of phase change cells. In this study, we developed two solutions to address the issue associated with conventional PCM programming circuits. We also analyzed conventional programming circuit schemes and designed a PCM programming circuit with improved speed using the SMIC 40 nm CMOS process. The results demonstrated that compared with conventional programming circuits, the PCM programming circuit with improved speed reduced the rise time of SET pulses from 29.6 ns to 7.3 ns and the rise time of RESET pulses from 13.6 ns to 3.1 ns. In addition, it improved the consistency of the programming phase change cells and reduced the power consumption from 11.93 mW to 10.35 mW.

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