Low power technique for testing VLSI circuits

Le résumé fourni par la source

In VLSI circuits as the density of transistors is increasing day by day testing of such large circuits is becoming a major tedious and challenging issue for our DFT Engineers. Fabrication processes are progressively becoming more intricate as an outcome of the emergence of deep submicron technologies. The features in current VLSI designs are becoming smaller, thinner, and closer, thereby increasing the likelihood of wire contact or breakage, which can lead to errors or faults in a circuit. The production of intricate integrated circuits (ICs) containing N number of transistors on one single chip necessitates verifying their functional accuracy. DFT usage, in the examination of a circuit, is a customary selection. This technique creates a collection of regulations governing the design process, ensuring the resulting circuit is readily testable. The proposed structure is used for testing a 5-input Digital Circuit by Low Power usage.

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