Effective Data-Width Aware ECC Scheme for HBM

Le résumé fourni par la source

High-bandwidth memory (HBM) has been developed for high-performance computing. For high reliability, some soft errors are corrected by the error correcting codes (ECC) on the memory die. However, the error correctability of on-die has limitations, necessitating methods to achieve higher reliability. A novel method is proposed that utilizes zero parts in DQ-data as ECC check bits and uses metadata as flags to indicate zero-part locations for improved ECC reliability. This method also implements Hamming ECC code on the base die for effective error correction, ensuring the integrity of CRC bits to the host. Experimental results show that this approach achieves high reliability when zero parts are included in addressing errors that occurred in the memory die and through silicon vias (TSV) with low hardware overhead.

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