A Dual-Band High-Efficiency Power Amplifier in 65-nm CMOS Technology

Le résumé fourni par la source

In this paper, a dual-band high-efficiency power amplifier (PA) in 65-nm CMOS technology is designed. The coupler-capacitor network realizes frequency reconfiguration and power division at different ports with the change of frequency automatically in broadband. The powercell adopts a cascode structure to achieve high output power. The PA consists of coupler-capacitor networks, a high-band network and a low-band network. The high-band network consists of a driver stage and a power stage to enhance gain flatness and expand bandwidth. The simulated 3-dB bandwidth(BW) of low-band is 65% (5.5 GHz-10.8 GHz), and the high-band is 54%(15.5 GHz-27 GHz). The proposed PA demonstrates 19.5 dBm saturated output power$(\mathrm{P}_{\text{sat}})$with a peak power-added efficiency (PAE) of 40% at 8 GHz and 16.8$\text{dBm}\mathrm{P}_{\text{sat}}$, 18.6% PAE at 21 GHz.

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