Strain Engineering for Highly Scaled MOSFETs

Le résumé fourni par la source

The advent of novel materials for manufacturing and the inherent constraints of nanoscale devices, which lead to an increase in the unpredictability of device characteristics, pose severe obstacles to the manufacturing of advanced ultra-scaled micro- and nanoelectronic devices. Power dissipation and a circuit's tolerance to process fluctuations present other significant design difficulties due to aggressive scaling. To boost metal–oxide–semiconductor field-effect transistors (MOSFETs) electrical performances, stress and strain engineering are nowadays used in all advanced semiconductor technologies. Future generations of complementary metal–oxide–semiconductor (CMOS) technologies will continue to rely on strain engineering as one of their primary performance enablers. The fifth generation of stress-engineering techniques with very high-stress levels has been demonstrated in advanced devices with nonplanar structures like trigate FinFETs, or nanowires, gate-all-around (GAA) nanowires, and nanosheet transistors. In this chapter, we shall discuss the functioning of strain- and stress-engineered MOSFETs, process-induced stress, and electrical characteristics of the strain-engineered semiconductor device. In this chapter, three-dimensional (3D) strain simulation case studies will be considered in several nanoscale device structures involving stressors on the channel strain profiles. We describe 3D quantitative descriptions of strain and stresses in the structures using numerical models based on the finite element method (FEM) that have undergone experimental validation. We shall attempt to give some insight into the process and device design via technology computer-aided design (TCAD) simulations and the optimization of strain-engineered MOSFETs. The present status and future trends in the strained-Si and high-mobility III-V semiconductor materials and devices will be briefly reviewed. We will also discuss the difficulties in integrating innovative materials and implementation strain on Si-based devices. This chapter aims to provide the reader with a comprehensive understanding of the device design and technology development for stress- and strain-engineered nanoscale devices.

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