28.5 A 94.1%-Efficiency Parallel-SC Hybrid Buck Converter Designed Using VCR-Aware Topology Optimizer for a 4.2A/mm² Current-Density FoM
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Increasing power density—delivering more power in a smaller footprint—stands as a pervasive trend across multiple markets, including the sector for buck DC-DC converters. One of the cardinal challenges in achieving optimized power density is navigating the intrinsic trade-off between an inductor’s volume and its parasitic DC resistance (DCR); miniaturizing the inductor invariably leads to elevated DCR. To enhance efficiency even when using compact inductors, many hybrid buck converter topologies have been investigated [1–4]. These hybrid inductor-capacitor innovations aim to mitigate inductor current $\left(I_{L}\right)$ by means of additional capacitive power delivery. A straightforward method for designing hybrid converters involves substituting one switch in a switched-capacitor (SC) converter with an inductor. As illustrated in the upper-left of Fig. 28.5.1, employing this design methodology enables the derivation of four distinct hybrid designs (H 1 to H 4) from a basic 2:1 SC converter. In most hybrid converters, the flying capacitor $\left(C_{\mathrm{F}}\right)$ is charged by $I_{\mathrm{L}}$ during the on-duty cycle $\left(D \times T_{\mathrm{S}}\right)$ and discharges its capacitive current, $I_{\mathrm{C}}$, to the output $\left(V_{0}\right)$ during the off-duty cycle $\left[(1-D) \times T_{\mathrm{S}}\right]$. Accordingly, the duty-cycle ratio $(D)$ is critical in determining both $I_{\mathrm{L}}$ and $I_{\mathrm{C}}$. As exemplified in the H 3 and H 4 topologies (top right of Fig. 28.5.1), a low D leads to a negligible reduction in $I_{\mathrm{L}}$, thereby losing the benefits of a hybrid converter. Conversely, when D is too high, $I_{\mathrm{C}}$ is prone to excessive surges because of the overcharging of $C_{\mathrm{F}}$ during an extended $D \cdot T_{\mathrm{S}}$, which in turn makes $I_{\mathrm{C}}{ }^{2}$-related conduction loss dominant. Optimal balance in the delivery of $I_{\mathrm{L}}$ and $I_{C}$ can thus be achieved when $D \approx 0.5$. It is worth noting that D also influences the voltage conversion ratio (VCR). The bottom right of Fig. 28.5.1 shows the H 1 to H4’s conduction losses, normalized to those in a typical buck converter. Herein, the optimal VCR at which $D(=0.5)$ is balanced is denoted as $V C R_{\text {opt. }}$. Interestingly, it can be seen that the minimum loss point for each hybrid design closely aligns with $V C R_{0 p t}$. Therefore, for maximum efficacy of a hybrid converter, the topology should be designed such that the target VCR ($\left.V C R_{\text {Target }}\right)$ matches $V C R_{0 p t}$.
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DOI retrouvé dans Crossref DOI retrouvé ; titre concordant.
- Titre Crossref
- 28.5 A 94.1%-Efficiency Parallel-SC Hybrid Buck Converter Designed Using VCR-Aware Topology Optimizer for a 4.2A/mm² Current-Density FoM
- Date Crossref
- 18/02/2024
- Éditeur
- IEEE
- Type
- proceedings-article
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Korea Advanced Institute of Science and Technology pays non établi dans la noticeUniversité ou école supérieure
Korea Advanced Institute of Science and Technology.
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