A Synopsys TCAD-based workflow to support technology evaluation at 3nm and beyond

Le résumé fourni par la source

Technology evaluation of new nodes is becoming increasingly complex; where transistor performance was once the critical metric, technology evaluation currently requires more complex metrics such as AC power and area. We present a method to utilize Synopsys TCAD to generate HSPICE collateral from device and process simulation to enable circuit simulation. This workflow is automated to support generation of packaged standard cell library collateral, enabling early analysis of more complex circuits which utilize automated routing tools to create. This workflow enables a much more accurate and complete picture of technology performance in a faster way than traditional PDK-based workflows.

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