Demonstration of Analog Compute-In-Memory Using the Charge-Trap Transistor in 22 FDX Technology

Résumé fourni par la source

Most analog compute-in-memory (CIM) devices suffer from low on/off ratio, large IR drop, limited retention capability, the need for an additional access device, and additional process complexity for embedding in commercial CMOS logic. To overcome these disadvantages, the charge-trap transistor (CTT) has been proposed. It uses commercial off-the-shelf technology (22 FDX demonstrated in this work) with no additional process cost or complexity. By biasing the CTT in the subthreshold regime, >105on/off ratio is achieved with a very high off-state resistance >$10^{11} \boldsymbol{\Omega}$. Up to 3% programming accuracy has been demonstrated. A twin-cell design is adopted to enable bipolar weight encoding with up to 4 equivalent number of bits (ENOBs). We deploy in-hardware vector-matrix multiplication (VMM) using the CTT as a combined weight storage element and switch and demonstrate excellent weighted-sum functionality with <2% error. CTT shows negligible retention loss and insignificant error degradation up to 85°C.

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