Analysis of a clock‐recovery technique for circuit emulation services over packet networks

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Abstract One important requirement of circuit emulation services (CES) over packet networks is clock synchronization and timing distribution among the nodes. CES depends on reliable and high‐quality timing for operations. In the time division multiplexing (TDM) world, whether plesiochronous digital hierarchy (PDH), synchronous digital hierarchy (SDH) or synchronous optical network (SONET) based, timing and synchronization is inherent in the design of the network. However, when timing critical services such PDH and SDH/SONET are carried over packet network (e.g. IP, Ethernet, etc.), the timing element is lost and has to be carried across the packet network by other means. A well‐known and widely implemented technique for clock recovery in CES is one that is based on packet inter‐arrival time (sometimes called time difference of arrival) averaging. The technique is very simple to implement but provides good performance only when packet losses and packet delay variation (PDV) are very low and well controlled. This technique has been extensively analysed through simulations but has not been fully characterized analytically with correlated traffic in the literature. In this paper, we provide a full analytical examination of this well‐known clock recovery technique. We analyse the effects of correlation of the delay variation in the traffic stream on the quality of the clock recovered by a receiver. We prove analytically that, for a general input process, high correlation of the delay variation produces a large variance of the recovered clock. Copyright © 2007 John Wiley & Sons, Ltd.

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