3D Integrated Pixel Sensor with Silicon-on-Insulator Technology for the International Linear Collider Experiment

Le résumé fourni par la source

The international linear collider (ILC) experiment requires a vertex detector which is characterized by low hit occupancy, low material budget, high-speed readout and high spatial resolution better than 3 /xm. A high functional signal readout circuit and multi-analog memories have been implemented in a 20 × 20 μm,2pixel with our 3D integration technology, Au micro-cylinder bump bonding, to maintain the spatial resolution. The material budget is lower than the conventional hybrid pixel detector used for high energy accelerator physics experiment by integrating monolithic pixel sensors, which are processed by Silicon-on-Insulator (SOI) technology. A 3D-integrated chip consists of two SOI pixel chips. The upper and lower chips are connected by Au micro-cylinder bump bonding instead of the generally used through silicon via (TSV). Analog and digital signals from the lower pixel are sent to the upper pixel via 3 /xm-diameter bumps. We have successfully demonstrated images of /3-ray tracks of 90 Sr by our prototype chip, SOFIST4, with a bump connection yield of 99.9 %.

Ce résumé expose les affirmations des auteurs. BNTIC ne l’interprète pas comme une validation indépendante des résultats.