A High Data Rate Swing Enhanced CMOS Pulse Generator with an Overhead Reducing Technique

Le résumé fourni par la source

A high data rate CMOS pulse generator employing an overhead reducing technique for wireless interconnect applications is designed in 90 nm CMOS technology. A maximum data rate of 14.2 Gbps can be achieved with the topology where the generator dissipates no static current with a relatively low energy figure of 1.8 pJ per pulse from 1.2 V supply rail. A train of on-off-keying modulated Gaussian monocycle pulses of an average duration of 72 ps having a high peak-to-peak amplitude of 1387 mV are generated by implementing the architecture with a RF simulator. The amplified voltage swing and enhanced transmission data rate compared with reported circuits make the low overhead architecture effective and suitable for use in short and medium distance wireless communication protocols.

Ce résumé expose les affirmations des auteurs. BNTIC ne l’interprète pas comme une validation indépendante des résultats.