A novel FPGA implementation of Hough Transform for straight lane detection

Résumé fourni par la source

Hough Transform (HT) algorithm is commonly used for linear detection but requires huge memory and computational complexity. In this paper, we design an adapted hardware architecture of HT for straight lane lines detection. Because the lane markings parallel in the 3D world cannot be horizontal or vertical in the image plane, we optimize the architecture and the computational complexity of HT. The proposed architecture uses (Y-intercept, θ) parameterization for the construction of HS and lane orientation, which also simplifies the inverse HT (IHT) operation and reduces the dimension of the accumulator. The efficiency of the proposed architecture is demonstrated by a software-hardware co-simulation on a Xilinx Virtex-5 ML505 platform. Compared to other reported hardware implementation, the proposed method can reduce the circuit resources. The processing speed is 1.47ms and the detection rate is 92%.

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