A 2.4 GHz gain-boosted CMOS amplifier using multibias points for improved linearization

Le résumé fourni par la source

A highly linear two stage CMOS amplifier using 130 nm technology is presented. A linearization technique is employed using multibias points through a combination of bulk bias control and floating bulk devices to achieve significant improvement of intercept points. Forward gain boosting is ensured by utilizing a cascode topology followed by a common source stage while maintaining a low ceiling for noise in the S band. Including a bias controlled feedback path between the stages further improves the architecture's expected gain compression. The final design reports 27.6 dB simulated power gain with third order input intercept of 9.92 dBm and noise figure of 1.22 dB at the center frequency. Input and output impedances have been matched with the help of passive appendages to ensure −24 dB input return loss and −27.5 dB output return loss, respectively. Optimized radio frequency parameters are achieved along with a linearity upgrade which is better than reported CMOS amplifiers.

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