Architecture of a synchronized low-latency network node targeted to research and education

Le résumé fourni par la source

As line-speeds and packet losses are sufficient well for most applications, reduction of latency and jitter are gaining in importance. We introduce and discuss the architecture of a novel networking device that provides low-latency switching and routing. It integrates an up-to-date FPGA with a standard ×86-64 processor and targets Time-Sensitive Networking (TSN) and machine-to-machine communication (M2M). First results show a cut-through latency of 2 - 2.5 μs for its 12 Gigabit Ethernet ports and full line rate packet processing. It features frequency synchronization across networks and is easily extendable, enabling researchers to build experiments in areas like industrial, automotive, and 5G mobile access networks, with highest precision, repeatability, and ease.

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