Pulse-Width Modulated Z-Source Neutral-Point-Clamped Inverter

Le résumé fourni par la source

This paper presents the careful integration of a newly proposed Z-source topological concept to the basic neutral-point-clamped (NPC) inverter topology, for designing a three-level inverter with both voltage-buck and -boost capabilities. The designed Z-source NPC inverter uses two unique X-shaped LC impedance networks connected between two isolated dc input power sources and its inverter circuitry for boosting its ac output voltage. Through the design of an appropriate pulse-width modulation (PWM) algorithm, the two impedance networks can be short-circuited sequentially (without shooting through the inverter full dc link) for implementing the "nearest three vectors" (NTV) modulation principle with minimized harmonic distortion and device commutations per half carrier cycle, while performing voltage-boosting. With only a slight modification to the inverter PWM algorithm and by short-circuiting the two LC impedance networks simultaneously, the designed NPC inverter, with no requirement for dead-time delay, can also be operated with completely eliminated common-mode voltage. Implementation-wise, detailed vectorial analysis interestingly shows that the same generic set of carrier-based modulation expressions can be used for controlling Z-source two-level inverter and NPC inverter with and without reduced common-mode (RCM) switching. All findings presented in the paper have been confirmed in simulation and experimentally using an implemented laboratory prototype.

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