Clock management in a Gigabit Ethernet physical layer transceiver circuit

Le résumé fourni par la source

This paper describes the clock management of a mixed signal, high-speed, multi-clock, fully synchronous circuit. The MA1111A13 circuit clock distribution is a complicated structure that seamlessly incorporates different well-known techniques for power reduction, asynchronous clock domains inter-operability, and compatibility with different IO timing standards and data rates. This complex clocking scheme has been successfully integrated into the standard semi-custom physical design flow. The physical implementation of the clock network with Synopsys Astro is also presented. 1.

Ce résumé expose les affirmations des auteurs. BNTIC ne l’interprète pas comme une validation indépendante des résultats.