A cache-aware motion estimation organization for a hardware-based H.264 encoder

Résumé fourni par la source

The video resolution required for many types of video content has increased as technology has advanced. For the real-time encoding of the high resolutions such as full high definition (FHD), quad-FHD (QFHD) and beyond, various fast motion estimation (ME) algorithms have been researched. Caches are used for many fast MEs in a hardware-based encoder, in order to increase local memory utilization and thereby reduce external memory access. However, most previous works do not pay attention to the amount of cache access from multiple MEs. In a multi-core environment for high resolution videos, access conflicts directly affect the computation time. In this paper, various types of caches are compared in terms of the size, hit ratio, cache port conflicts and hardware overhead. To reduce the amount of cache access associated with the basic shared cache, zigzag snake scan and selective data-storage schemes are proposed for integer and fractional MEs, respectively. Additionally, the cache access arbitration hides the computation delay which arises due to a cache port conflict in a pipeline system. The proposed schemes are applicable for the existing cache design achieving a good scalability in a multi-core environment. Simulation results show that the ME computation time reduced by the proposed schemes is comparable to that of the dual-port shared cache which shows the least amount of port conflicts.

Ce résumé expose les affirmations des auteurs. BNTIC ne l’interprète pas comme une validation indépendante des résultats.