The design of a high-resolution CMOS comparator

Le résumé fourni par la source

The authors describe the design of high resolution CMOS comparators by firstly presenting an analysis of comparators with and without the cross-multiplexed technique (XMT). Analytic formulas for the comparison time and the setup time of the comparator are derived. The comparison times calculated are very close to those obtained using SPICE simulation for large coupling capacitances between stages. For small coupling capacitances, the effect of charge-pumping becomes significant and leads to a deviation of the predicted comparison times from those obtained using SPICE simulation. However, the use of XMT, which increases the effective input voltage and thus reduces the charge-pumping effect, leads to a closer agreement between the calculated and simulated comparison times, as well as a significant reduction in the comparison time for cases with small coupling capacitance, where the magnitude of error voltage due to charge pumping is larger. A design example shows that it is possible to implement a CMOS comparator with an input-voltage resolution of less than 100 mu V and a maximum comparison time of less than 2 mu s using XMT.>

Ce résumé expose les affirmations des auteurs. BNTIC ne l’interprète pas comme une validation indépendante des résultats.